1. Field of the Invention
The present invention relates to a semiconductor device comprising through electrodes and a semiconductor module employing thereof.
2. Related Art
In the conventional technique, bare chip stacked-type multi-chip module (MCM) has been proposed for the purpose of achieving higher degree of integration over a SiP of a package stacked-type or a type of having arranged chips in parallel. An interconnect extending through the semiconductor substrate is essential for the bare chip stacked-type module. Exemplary conventional bare chip stacked-type MCMs having a through electrode are described in Japanese Patent Laid-Open No. 1998-223,833 (H10-223,833), Japanese Patent Laid-Open No. 2002-170,904, Japanese Patent Laid-Open No. 2002-289,623 and Japanese Patent Laid-Open No. 2002-43,502.
Japanese Patent Laid-Open No. 1998-223,833 and Japanese Patent Laid-Open No. 2002-170,904 describe semiconductor devices comprising columnar plugs that extend through the semiconductor chips. In the semiconductor devices described in Japanese Patent Laid-Open No. 1998-223,833 and Japanese Patent Laid-Open No. 2002-170,904, one interconnect is disposed corresponding to one opening of the semiconductor substrate having a plug embedded therein.
Japanese Patent Laid-Open No. 2002-289,623 discloses a structure, in which duplex insulating films are provided to enclose a conductive plug having a columnar shape and extending through a semiconductor region. Such configuration is provided by, firstly, providing a conductive via, and providing an insulator trench ring on the surface of the semiconductor substrate that is disposed outside of the conductive via, thereby forming the via structure comprising the duplex insulating films. It is described that forming of the duplex insulating films is helpful in inhibiting defect of insulation or defect of coupling between the bump bonding area and the semiconductor substrate.
Japanese Patent Laid-Open No. 2002-43,502 describes an exemplary via including duplex conductive films, which has a structure of leaving a column of silicon in the center thereof. It is described that the filling characteristics can be improved by employing the multiple structure for the ring-shaped slit via. Japanese Patent Laid-Open No. 2002-43,502 also discloses a chip for a semiconductor device having an electrically insulated ring-type Cu chip through plug. The ring-type chip through plug is formed by forming a ring-shaped concave portion so that a convex Si wafer is remained therein, providing a Cu film on an insulating film covering each of the side faces and a bottom face of the concave portion, and filling the concave portion by conducting an electrolytic plating technique from the Cu film as a starting point.
Japanese Patent Laid-Open No. 2002-43,502 also describes a configuration for forming duplex slit vias by a method, in which, when a ring-shaped slit via is filled up with Cu, the filling is not completed, and a slit of formed gap is filled with an insulating material. It is described that the time required for filling can be reduced by having the ring-shaped chip through plug, as compared with the case of filling the pipe-shaped concave portion. In addition, it is also described that an amount of the deposition required for filling the through hole with metal can be reduced to improve the throughput. It is also described that the bonding area between the chip through plug and the coupling electrode can be increased, so that the deterioration of the reliability can be inhibited.